The implementation of hardware neural net systems

Describes a multilayer pipelined digital architecture suitable for the implementation of large neural nets (LN) for vision applications. It can also be used to do some pre-filtering, such as pixel averaging, by setting weight values appropriately. A 1024 node processor with a clock rate of 10 MHz can operate on an input vector consisting of 32*32 8 bit pixels in 102 mu s. It can therefore process a 256*256 pixel frame in about 6.5 ms, which is well within the requirement for real-time processing, given a frame update rate of 20 ms. The architecture is currently being assessed to see how it can be extended to perform other image processing applications, and other NN training algorithms.<
>