Circuit partitioning with partial order for mixed simulation emulation environment

A low-cost hybrid simulator for VLSI circuits has been under development at IIT Delhi. The simulator uses a Reconfigurable System (RS) consisting of a limited number of FPGAs for hardware emulation and blends the ideas of hardware emulation with conventional software simulation. A crucial preparatory step is to partition a given circuit into as few parts as possible. The parts are then downloaded onto the RS one by one and emulated in stand alone mode or in conjunction with software simulator. The hybrid simulation environment poses some unique requirements on the partitioner. This paper presents can efficient partitioning algorithm for this purpose. A study of performance of the algorithm on 92 benchmark circuits for various I/O and size constraints of FPGAs has been carried out and good results have been obtained.