Arithmetic built-in self-test for digital signal processing architectures

In this paper, we present a new non-intrusive built-in self test (BIST) methodology, aimed at improving testability of DSP architectures. The method utilizes the arithmetic blocks in DSP data paths to perform test pattern generation and test response compaction. Consequently, it requires virtually no area overhead and results in no performance degradation. Furthermore, it can be used for at-speed testing thereby providing a capability to detect failures that may not be detectable by conventional low speed testing.