Technology decomposition for low-power synthesis

Technology decomposition and technology mapping are two potential stages for minimizing circuit power during logic synthesis. Since power in CMOS circuits is directly dependent on the extent of circuit switching activity, we present a novel procedure to construct a low-activity circuit structure in the technology decomposition stage. This would result in low-power circuits when mapped. The algorithm uses the transition density as a measure of switching activity and is applicable to both synchronous and asynchronous static circuits. Our results show power reductions of up to 48% (on average /spl ap/10%), with little area or delay penalty.