Standardizing ASIC libraries in VHDL using VITAL: a tutorial

VITAL originated as an industry driven effort to standardize VHDL models for ASIC libraries. An IEEE version of VITAL is expected by the end of 1995. In this tutorial, after examining the goals behind the development of this standard, I shall discuss its central features using examples of VITAL-compliant models. Throughout, I shall concentrate on those aspects of VITAL which affect the development of ASIC models, and only touch on those which affect VHDL simulation development. Models using several VITAL-compliant styles are presented and discussed.