High-speed low-power integrating CMOS sample-and-hold amplifier architecture

A novel "current-mode" sampling architecture for sample-and-hold (S&H) amplifiers results in a substantial reduction in error due to sampling clock jitter and aperture time. These reduced errors make possible a substantial reduction in power over a conventional "voltage mode" S&H with the same sample rate. In order to demonstrate the performance of this architecture, a S&H with 4 subsampled parallel outputs has been designed using less than 2 mm/sup 2/ die area in a 1.2 /spl mu/ CMOS process. Operating at 100 MS/s the circuit dissipates only 25 mW of power. Integral nonlinearity of the S&H circuit is less than 0.4%. Simulation results of the second generation S&H circuit with improved common-mode rejection are also presented.