An efficient contact placement for custom cell layout synthesis

This paper presents a new method for determining the number of required contacts and positions in the diffusion areas of transistors. An analytical model for effective transistor size is introduced as a function of contact design. In particular, we present algorithms to determine an optimum number of contacts that are required to meet circuit designer's specifications on the effective transistor size. A large transistor layout with various contact numbers is used to illustrate the importance of contact design. A contact placement and routing algorithm is developed and applied to generate the physical layouts of logic cells in MCNC standard cell library with efficient contact design.