On-chip cross talk-the new signal integrity challenge

Deep submicron digital CMOS circuits are exposed to a new signal integrity challenge, the on-chip crosstalk. Omitting the effects of crosstalk can lead to functional failure of these devices. Due to CMOS chip complexities manual analysis and interconnect changes are impractical and an automated tool is required. The paper describes a practical CAD solution to the problem after giving a detailed discussion of modeling the on-chip crosstalk.