A power optimized 13-bit 5M samples/s pipelined analog to digital converter in 1.2 /spl mu/m CMOS

A 13-bit 5-MHz pipelined analog to digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier architecture and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 /spl mu/m CMOS process displayed 80.1 dB peak SNDR and 82.9 dB dynamic range. INL is 0.8 LSB and DNL is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply.