Circuit technique for skew-free clock distribution

This paper describes a low-skew clock distribution technique for multiple targets using an automatic skew-compensation circuit. Using this technique keeps clock skew among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 0.9 ns is cancelled automatically and 30 ps clock skew is achieved at a clock frequency of up to 250 MHz with 60 ps clock jitter.