Special memory and embedded memory macros in MPEG environment

Special memory and embedded memories used in a newly designed MPEG2 decoder LSI are described. Orthogonal memory is employed in a IDCT (Inverse Discrete Cosine Transform) block for small area and power. FIFOs and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder are also described.