Hot-carrier induced degradation of critical paths modeled by rule-based analysis

An implementation of simple hot carrier rules is presented with the intent of providing insight into reliability problems as early in the design process as possible. To that end, these rules have been incorporated into BERT, a circuit reliability simulator, using a timing simulator as the simulation engine. This allows for quick estimation of problem points in the critical path of large circuits. Furthermore, by exploiting the inverting property of CMOS circuitry, it is possible to remove some of the estimation problems that can arise from false paths. By separating analysis into rising and falling waveforms, and partitioning the circuit into channel connected components, it is possible to prevent analysis of clearly impossible paths.