On the Scaling of Flash Cell Spacer for Gate Disturb and Charge Retention Optimization

Self-aligned contact processes enable aggressive scaling of the cell sidewall spacer for advanced nor Flash technology. Spacer scaling can increase bake-induced charge loss/gain and gate disturb. High-quality spacer dielectrics are necessary to reduce the bake shift and gate disturb effects. The peak field at the floating gate corner, in particular, plays a significant role in gate disturb.