Interconnect Modeling: A Physical Design Perspective

Variability, reliability, and design size are becoming major difficulties in system-on-a-chip (SoC) designs as the scaling of semiconductor technology advances. Techniques for interconnect modeling and analysis in designing advanced SoCs are discussed from the design-automation point of view. Importance of interconnect modeling in modern chip-design flows is first summarized. State-of-the-art physical-design techniques for parasitic extraction, signal-integrity analysis, and timing analysis (which are commonly executed throughout the final verification of physical design) are then reviewed. The extraction and analysis require the most accurate process information and modeling. Requests with respect to the manufacturing-design interface are discussed, and the authors' perspective concerning future SoC physical designs is addressed with emphasis on interactions between manufacturing and design technologies.