Second-Bit-Effect-Free Multibit-Cell Flash Memory Using $\hbox{Si}_{3} \hbox{N}_{4}/\hbox{ZrO}_{2}$ Split Charge Trapping Layer

In this paper, a Si
₃
N
₄
/ZrO
₂
split charge trapping layer (SCTL) is proposed for multibit-cell Flash memory. The complementary potential wells of Si
₃
N
₄
/ZrO
₂
storage nodes enable independent node control when the Fowler-Nordheim (F-N) method is applied for programming/erasing (P/E). Experiment and simulation results suggest that the 2-bit (2-b) charge storage is accomplished by physical data node separation for the SCTL rather than charge injection control. The well-confined charge storages suppress the second-bit effect, enabling excellent 2-b data clearance for short-channel SCTL devices. It was found that the remaining memory windows after 10
⁵
s decrease, dependent on the difference of the trap properties between Si
₃
N
₄
and ZrO
₂
.