A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique

A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3 times VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to 140/120/120/120/80/40 Mbps for 5/3.3/2.5/1.8/1.2/0.9 V, respectively, with a given capacitive load of 10 pF.