Polynomial delay models for optimisation-based transistor sizing in digital CMOS VLSI circuits

Numerical optimisation of VLSI circuits, has evolved as an important tool to achieve short design times for full custom digital MOS circuits. For optimising critical path delays, accurate modelling of signal delay is of special importance. Although device level simulators like SPICE produce accurate and detailed delay information, analytical delay models are required in general, since SPICE computation times increase rapidly with the number of transistors in the circuit. The authors present accurate gate level delay time models for CMOS logical circuits. The computation speed improvement of delay calculation is at least two orders of magnitude. Circuit elements can be inverters, M-input-NAND and NOR-gates and CMOS transfer gates.<
>