Energy efficient DSP architectures for VSELP speech coder

One of the primary objectives in the design of digital portable radio is power reduction required to maximize run time and minimize battery size and weight. Available power saving strategies such as dynamic power level control and discontinuous transmission are limited in their scope. A more effective approach is to operate the processors at the lowest supply voltage without incurring reduction in the throughput. Parallel architecture utilizing pipelining and parallelism through hardware duplication can be used to maintain throughput at lower voltages, by allowing slower device speeds. In the paper, several parallel/pipelined implementations of a VSELP speech coder employing VSELP algorithm modifications are suggested and are assessed for the power saving-voice quality trade-off.