Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks

In this paper we propose a new approach to the problem of estimating worst-case power consumption of CMOS combinational circuits based on neural models. Given the gate level description of a circuit, we build the corresponding neural network, we store it, we calculate the energy dissipated by the network and, finally, we derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain; that is, Algebraic Decision Diagrams are used to represent and manipulate the graph specification of the neural network modeling the circuit. We present preliminary results to show the feasibility of the method.