Single-transistor transparent-latch clocking

We propose a single-phase clocking scheme for CMOS VLSI designs in which the traditional master-slave data-latches are replaced with transparent-latches where each transparent-latch is implemented using a single NMOS transistor. The clocking scheme places a constraint on the allowable width of the clock pulses which can be satisfied by a clock driver that is integrated with a dynamic buffer. Our example shows that the power dissipation of the single-transistor latch can be 80% less than the two-phase static flip-flop and 70% less than the true single-phase latch. The low power dissipation of the single-transistor latch can therefore be used to improve the gain in architecture-driven voltage scaling where one reduces the supply voltage to reduce power dissipation and applies pipelining to compensate for the reduced speed. In our example, the fraction of power dissipation due to the overhead of the pipelining latches for the single-transistor latch is only 4.7%, versus 15% and 22% for the true single-phase latch and the two-phase static flip-flop, respectively. The single-transistor latch is also very small, which can have a major impact in reducing the area of latch-intensive architectures such as filter structures used in digital signal processing. Our example of a fixed-coefficient transposed-form FIR filter shows that we can reduce the area by 20% in comparison to designs using the true-single-phase latch.