A post-processing algorithm for short-circuit defect sensitivity reduction in VLSI layouts

Yield enhancement may well be regarded as the quintessential objective in microelectronic manufacturing. With diminishing feature size and increasing die area the amount of functional silicon on a die is too expensive to discard in the event of short-circuit and open-circuit faults. Designing chips with high tolerance against faults, therefore, holds a great promise for profitable manufacturing in the semiconductor industry. In this paper we propose a post-processing defect-tolerant routing algorithm that reduces or eliminates short-circuit sensitive area, and minimizes vias in a two-layer channel routing solution. The algorithm is built to be sensitive to manufacturer's defect pareto figures. This feature gives the designer the flexibility of customizing the routing algorithm to the desired defect-tolerant features without increasing the die area or interconnect length.