Innovative design of CMOS fault tolerant structures

A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and the complemented form of the desired output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they cause the two output lines to share the same value. This latter characteristic allows design of self-checking gates (with respect to faults that are not tolerated). Usually, production of the natural and complemented form of the output signal does not require to double the number of transistors, thus resulting more convenient (in terms of area) than other approaches; moreover the cost overhead due to the implementation of both the natural and the complemented form of the output decreases with the size of the gate. Therefore the proposed structure may be conveniently adopted in full-custom design of large fault tolerant systems, since in this case the gate size can be modified to achieve the best trade-off between speed and area overhead.