Yield management in microelectronic manufacturing

Semiconductor technology trends continue to drive toward cheaper, faster, denser, lower-power, and more reliable products. These trends are however, neither independent of nor conducive to each other. Faster and denser designs, for example, increase power, reduce yield and reliability, and increase cost. In many cases, a trade-off is made between cost and performance. The prime factor in determining the cost of a product is its manufacturing yield. It has hence become increasingly important to understand the intricate relationships between process technology, product design, manufacturing tools, and yield. The ability to predict yield long before the product is manufactured is fundamental to a decision-making process during the development phase. Accelerated yield-learning is the next step to reducing the development-to-market time and product cost. Several disciplines should progress coherently to define a yield plan and assure meeting the desired yield targets. Special test structures are designed and tested for yield at different stages of the process to determine the dominant yield detractors, the nature of defects, their size and spatial distributions, and their impact on yield. Models are developed to extract yield parameters from test results and predict the product yield. Systematic and gross defects are mostly eliminated early in the development. The impact of random defect size and density increases with minimum feature size. Tool, process, and design changes are hence made to reduce the defect density to a level that can be tolerated by the specific design. Yield learning is vigorously pursued via measurements against the targets, establishing action plans and tightening the targets in a cyclical mode. The purpose of this paper is to describe the yield management methodology and to provide an overview of the steps required to analyze, predict, and accelerate the product yield learning. Practical examples based on memory and logic designs are discussed.