On-chip measurement of interconnect capacitances in a CMOS process

A new Test Structure for measurement of small constant capacitances is presented. As compared to previously published methods, improvements are obtained in the field of accuracy and resolution. No reference elements are used and the calculated capacitance is free of parasitic capacitance influence. Moreover, the Test Structure occupies a small area. It is particularly suitable for spatial scattering studies and for modelling of small dimension interconnect capacitances.