Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming

We propose a quadratic 0-1 approach to redesign a circuit in order to test it for excessive delays using a new robust delay-fault Built-In Self Testing (BIST) model. This approach models the problem as a weighted signed graph balancing problem. The algorithm has O(n/sup 2/) complexity, where n is the number of circuit nodes. We drop hardware from false timing paths to lower the delay fault BIST hardware overhead to 17% in large circuits (measured overhead in addition to stuck-fault BIST overhead). Results show that the computation is rapid for the 1985 ISCAS benchmarks.