An optimized testable architecture for finite state machines

This paper presents a testable architecture for FSM synthesis. The transfer, synchronizing and distinguishing sequences are obtained simultaneously by adding extra edges, if necessary, and their associated inputs and outputs to the original FSM. The algorithm that achieves this minimizes the number of extra edges that make a machine testable. The testable machine has the following properties: (1) transfer sequences of length at most [log/sub 2/n] where n is the number of the states in the machine, to carry the machine from state S/sub i/ to state S/sub j/ for all i and j, (2) a synchronizing sequence of length at most [log/sub 2/n] which sets the machine to a specific state S1, and (3) a distinguishing sequence of length at most [log/sub 2/n]. The states can be observed at the output. Several synthesis benchmark circuits were investigated for area by using the architecture.