Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique

In this paper a novel development of a testing technique for analogue integrated circuits based on sweeping the power supply voltage is described. It is shown that by using a simple floating gate fault model together with the proposed scheme it is possible to achieve a high fault coverage. The scope of work discussed in this paper is focused on exposing floating gate defects which, using other methods, usually requires careful and accurate knowledge of the elements, including parasitic components, of the equivalent circuit of the devices.