Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs

The introduction of multiplexer based FPGAs has renewed interest in logic design using multiplexers. This paper presents an iterative approach for the synthesis of combinational circuits using a tree network of 2-to-1 multiplexers. A characterizing parameter of Boolean functions, known as Ratio Parameters, has been used in each iteration to reduce the search space. The obtained multiplexer network is then mapped onto the Actel ACT1 FPGA basic blocks. The performance of the proposed approach has been evaluated by comparing the results of 11 MCNC benchmark problems with the results of the existing technology mappers.