Design considerations for implementing a modularly configured attached processor in a multi chip module

Implementation of a novel modularly configured attached processor (MCAP) architecture was evaluated using 1 /spl mu/m CMOS logic on an MCM-D The transistor count was approximately ten million transistors, distributed on twenty-five chip dice. Delay, area, and power calculations were performed using the SUSPENS model. Rent's rule was found to be not applicable. Speed was calculated to be in the 100 MHz range. The module foot print was found to be 90 cm/sup 2/. Power dissipation per unit area was low enough to allow air cooling.