A fold-back current-limit circuit with load-insensitive quiescent current for CMOS low dropout regulator

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic for CMOS low dropout regulator (LDO), is proposed in this paper. This method has been designed in 0.35 mum CMOS technology and verified by Hspice simulation. The quiescent current of the LDO is 5.7 mA at 100-mA load condition. It is only 2.2% more than it in no-load condition, 5.58 mA. The maximum current limit is set to be 197 mA, and the short-current limit is 77 mA. Thus, the power consumption can be saved up to 61% at the short-circuit condition, which also decreases the risk of damaging the power transistor. Moreover, the thermal protection can be simplified and the LDO will be more reliable.