23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration

A novel nonlinear foreground calibration of pipeline A/D converters based on LMS algorithm has been proposed and verified by macro-based simulation as well as measurement of test chip. The prototype 23-mW 50-MS/s 10-bit pipeline ADC in 0.13-mum CMOS has confirmed that the proposed calibration can accurately and rapidly correct the inaccuracy caused both by heavy nonlinearity of low-gain op-amps and by their incomplete settling without requiring any dedicated voltage references, complicated structures or timing sequence and hence can be used for various applications.