Hardware implementation of a low-complexity detector for large MIMO

Large MIMO systems represents an effective way to transmit reliably at very high data-rate, but their complexity still represents a problem for practical realization. This paper addresses the hardware implementation of a low-complexity and high-performance detector for a 32 times 32 MIMO. It allows to reach very high data rate, up to more than 170 Mbit/s with a 64 QAM with BER 10
^-1.5
-10
^-2
and constitutes a cost effective improvement over basic detection schemes.