Simulation study of Time-Average-Frequency based clock signal driving systems with embedded Digital-to-Analog Converters

The Flying Adder (FA) architecture is one of the latest developments in the area of on-chip frequency synthesis. It has two operating modes: integer-FA mode and fractional FA mode. In the fractional FA mode, a concept of Time-Average-Frequency is used to synthesize certain frequencies that cannot be easily obtained using traditional methods. The issue of using Time-Average-Frequency to drive digital systems has been studied in previous publications by the authors. In this paper, we investigate the impact of using Time-Average-Frequency based clock signals to drive systems with embedded Digital-to-Analog Converters (DAC).