Serendipitous SEU hardening of resistive load SRAMs

High and low resistive load versions of Micron Technology's MT5C1008C (128K/spl times/8) and MT5C2561C (256K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors was observed for the low resistive load SRAMs, which also exhibited a "1"/spl rarr/"0" to "0"/spl rarr/"1" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.