Time-multiplexed routing resources for FPGA design

We propose a time-multiplexed routing architecture for SRAM based FPGAs. This can be implemented by having two programmable SRAMs for each routing connection. The goal of this approach is to alleviate the on-chip routing bottleneck, and to increase the range of circuit sizes which can be accommodated on a single chip. We consider a Xilinx 4000 style architecture with and without time-multiplexed routing. Our experimental results show that time-multiplexed routing can reduce the channel density by 30%. Also, sharing permutation equivalent LUTs between the time phases can result in a 14% reduction of the number of LUTs required to implement a design.