Design of a chip set for a parallel computer based on the crossbar interconnection principle

Frequently found implementations of the parallel random access machine (PRAM) include the common-bus multiprocessor as well as shared-memory machines based on several types of switching networks. The performance of the common-bus multiprocessor decreases as the total number of required data exchanges among processors, for a given computation, grows. The same applies to switching networks but, because of the higher number of available data paths, to a lesser degree. In this sense, the advantages of the crossbar network as compared to other switching networks are well known. However, the high number of switching elements required by this network has been a limitation on its use in practical machines. In this paper, a variation of the crossbar network based on m(m-l) switching elements, where m is the number of processors, is discussed. The architecture of the machine is described, and the design of the chip set of the machine, based on field-programmable gate arrays (FPGA's), is presented. A brief description of the functions implemented in each device is given, followed by a detailed discussion of the switching elements, and, in particular, of the access priority arbitration function implemented in the device. Performance estimations of an 8-processor machine are presented and compared with a common-bus multiprocessor design using similar technology. It is concluded that the crossbar network represents a technologically viable alternative to other implementations of limited parallelism.