A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-/spl mu/m CMOS technology.