A full bit prefetch DRAM sensing circuit

A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAM's, 256-bit-long data I/O lines are divided into eight segments. A small local latch is provided for each segment of 32 bit-line pairs to prefetch eight data out of the 256 sense amplifiers. A local buffer is connected to eight local latches through selection switches. Burst read operations, up to eight bits, are done by activating selection switches and the local buffer serially. Besides this prefetch capability, the segmented data I/O line results in very small capacitance, only 0.09 pF. The sensing scheme uses nMOS bit switches and a full Vdd precharge voltage for bit and segmented data I/O lines. Then, after sense amplifiers are turned on, only low-going bit lines are connected to the segmented data I/O lines without any voltage disturbance because of the small capacitance. The proposed circuit, therefore, realizes a high-speed RAS access, which is 16 ns faster than a conventional DRAM. A circuit layout design based on a 0.5-/spl mu/m design rule shows no area impact.