Single event effect characteristics of CMOS devices employing various epi-layer thicknesses

Latchup resistant process, combined with SEU mitigation circuitry, may provide sufficient protection for many satellite applications. We report proton and heavy ion cross section measurements to illustrate the epitaxial layer thickness dependence on a First-in, First-out (FIFO) memory and microprocessor devices fabricated in a commercial CMOS/EPI process.