Extracting interconnect capacitance sensitivity to linewidth variation

VLSI interconnect capacitance is becoming more significant and also increasingly subject to process variation. A simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variations is proposed based on 2.5D capacitance models and implemented in the Magic VLSI layout editor. The derivative of each extracted capacitance with respect to variation in every level is obtained. Coincident edges in layout result in distinct “shrinking” and “bloating” derivatives. The derivatives form a gradient that may be multiplied by a vector of the variations on each level to give the total expected deviation from nominal capacitance. The gradient allows the process sensitivity of each capacitance to be determined by simply inspecting the netlist.