A low-voltage, low-power CMOS delay element

A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed.