A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 /spl mu/m digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy.