Mismatch modeling and characterization of bipolar transistors for statistical CAD

A simple test structure and an extraction methodology are presented to study the parameter mismatch variance for vertical npn bipolar transistors. Guidelines for precise and repeatable measurement are discussed, the importance of simultaneous measurement of parameter mismatch is also shown. Mismatch measurements made on 192 BJT pairs fabricated at Orbit, in their 2 /spl mu/m n-well CMOS process, are used to develop a BJT mismatch variance model and to predict the collector current mismatch deviation of the same population of BJT's. Comparisons are made with the measured collector current mismatch.