A Ti salicide process for 0.10 /spl mu/m gate length CMOS technology

The fundamental issues for extension of a Ti salicide process to 0.1 /spl mu/m gate length CMOS technologies are presented for the first time. We report the first process to achieve low sheet resistance of 4 /spl Omega//sq at an ultra-narrow 0.10 /spl mu/m gate length (with deposited Ti=27 nm for TiSi/sub 2/=50 nm). Successful implementation into a sub-0.18 /spl mu/m gate length CMOS technology is demonstrated.