Hybrid phase locked loop system for PRML disk drive read channels

This paper describes a mixed signal Phase Locked Loop sub-system in a Partial Response Maximum Likelihood (PRML) disk drive read channel IC fabricated on a single poly, dual metal 0.6 u, 5 V foundry CMOS process. The PLL provides programmable damping factor and gain control over a 25-200 MHz frequency range. A non-linear ADC improves its robustness when processing asymmetrical input signals. Acquisition time is reduced by instantaneously adjusting the start-up phase of its clock output.