A 500 MHz 1 Mb on-chip cache design using multi-level bit line sensing scheme

The article compares the overall delay between a conventional design scheme vs. this work for the same process technology. Separate write BLs and split read BLs reduce the first two timing components from 22 gd to 10 gd. A new SA design improves the sensing delay by 3 gd, and the differential dynamic implementation of sel mux/load aligner shaves 5 more gd from critical path. Therefore we conclude this design using multi-level sensing scheme can reduce 40 gd cycle time by conventional scheme down to 20 gd, achieving 500 MHz performance with today's technology.