A fully integrated low noise RF frequency synthesizer design for mobile communication application

A fully monolithic PLL frequency synthesizer circuit implemented in a 0.8 /spl mu/m CMOS technology is presented. The measured result shows a frequency range of 700 MHz to 1 GHz with -100 dBc/Hz phase noise at a 1 MHz carrier offset. The test chip consumes 125 mW at maximum frequency from a 5 V supply. No external components are used except a passive filter and supply decoupling capacitors.