The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

We have examined the effect of drain offset structures with lengths ranging from 0.0 /spl mu/m to 1.0 /spl mu/m on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of channel lengths studied (1.0 /spl mu/m to 0.35 /spl mu/m) the optimum drain offset length was 0.35 /spl mu/m.