Worst case analysis of low-voltage analog MOS integrated circuits

A methodology for worst case analysis of low voltage analog MOS integrated circuits is presented. It relates parameter to current mismatch in a transistor pair analytically and the current mismatch is regarded as a random variable. It is shown that the algorithm is efficient and is readily extended to the circuit level. The effect of the active area of critical transistor pairs is also investigated. The methodology is used to study the DC offset in low voltage CMOS op amps.