Receiver ASIC for timing, trigger and control distribution in LHC experiments

An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and make them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognising individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a PINFET preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1 /spl mu/m CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow to phase shift the system clock and the first level trigger accept signal up to a maximum of sixteen clock cycles in steps of 0.1 ns.